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-rw-r--r--cpp/include/IceUtil/Config.h8
-rw-r--r--cppe/include/IceE/Config.h9
2 files changed, 13 insertions, 4 deletions
diff --git a/cpp/include/IceUtil/Config.h b/cpp/include/IceUtil/Config.h
index 41bbcd39a57..b2bf91970f4 100644
--- a/cpp/include/IceUtil/Config.h
+++ b/cpp/include/IceUtil/Config.h
@@ -16,13 +16,17 @@
// Most CPUs support only one endianness, with the notable exceptions
// of Itanium (IA64) and MIPS.
//
+#ifdef __GLIBC__
+# include <endian.h>
+#endif
+
#if defined(__i386) || defined(_M_IX86) || defined(__x86_64) || \
defined(_M_X64) || defined(_M_IA64) || defined(__alpha__) || \
- defined(__MIPSEL__)
+ defined(__MIPSEL__) || (defined(__BYTE_ORDER) && (__BYTE_ORDER == __LITTLE_ENDIAN))
# define ICE_LITTLE_ENDIAN
#elif defined(__sparc) || defined(__sparc__) || defined(__hppa) || \
defined(__ppc__) || defined(__powerpc) || defined(_ARCH_COM) || \
- defined(__MIPSEB__)
+ defined(__MIPSEB__) || (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN))
# define ICE_BIG_ENDIAN
#else
# error "Unknown architecture"
diff --git a/cppe/include/IceE/Config.h b/cppe/include/IceE/Config.h
index 8fc9e62d211..6367a27a3a4 100644
--- a/cppe/include/IceE/Config.h
+++ b/cppe/include/IceE/Config.h
@@ -103,12 +103,17 @@
// Most CPUs support only one endianness, with the notable exceptions
// of Itanium (IA64) and MIPS.
//
+#ifdef __GLIBC__
+# include <endian.h>
+#endif
+
#if defined(__i386) || defined(_M_IX86) || defined (__x86_64) || \
defined (_M_ARM) || defined(__MIPSEL__) || defined (__ARMEL__) || \
- defined (__BFIN__)
+ defined (__BFIN__) || (defined(__BYTE_ORDER) && (__BYTE_ORDER == __LITTLE_ENDIAN))
# define ICE_LITTLE_ENDIAN
#elif defined(__sparc) || defined(__sparc__) || defined(__hppa) || \
- defined(__ppc__) || defined(_ARCH_COM) || defined(__MIPSEB__)
+ defined(__ppc__) || defined(_ARCH_COM) || defined(__MIPSEB__) || \
+ (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN))
# define ICE_BIG_ENDIAN
#else
# define ICE_LITTLE_ENDIAN