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| author | Dwayne Boone <dwayne@zeroc.com> | 2006-04-03 12:24:52 +0000 |
|---|---|---|
| committer | Dwayne Boone <dwayne@zeroc.com> | 2006-04-03 12:24:52 +0000 |
| commit | ab98fc07efbe0b5f7d09f53d423a0e161b7e7b83 (patch) | |
| tree | cdc330660002ca4aa09f6d6a0e47a75caba35a1a /cppe | |
| parent | minor fixes; new IceSSL plugin (diff) | |
| download | ice-ab98fc07efbe0b5f7d09f53d423a0e161b7e7b83.tar.bz2 ice-ab98fc07efbe0b5f7d09f53d423a0e161b7e7b83.tar.xz ice-ab98fc07efbe0b5f7d09f53d423a0e161b7e7b83.zip | |
Fixed bug 921 - added MIPS support
Diffstat (limited to 'cppe')
| -rw-r--r-- | cppe/include/IceE/Config.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cppe/include/IceE/Config.h b/cppe/include/IceE/Config.h index 1bcd826b5c7..9100b184acc 100644 --- a/cppe/include/IceE/Config.h +++ b/cppe/include/IceE/Config.h @@ -87,9 +87,11 @@ // Most CPUs support only one endianness, with the notable exceptions // of Itanium (IA64) and MIPS. // -#if defined(__i386) || defined(_M_IX86) || defined (__x86_64) || defined (_M_ARM) +#if defined(__i386) || defined(_M_IX86) || defined (__x86_64) || \ + defined (_M_ARM) || defined(__MIPSEL__) # define ICE_LITTLE_ENDIAN -#elif defined(__sparc) || defined(__sparc__) || defined(__hppa) || defined(__ppc__) || defined(_ARCH_COM) +#elif defined(__sparc) || defined(__sparc__) || defined(__hppa) || \ + defined(__ppc__) || defined(_ARCH_COM) || defined(__MIPSEB__) # define ICE_BIG_ENDIAN #else # error "Unknown architecture" |