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| author | Dwayne Boone <dwayne@zeroc.com> | 2008-06-04 14:01:55 -0230 |
|---|---|---|
| committer | Dwayne Boone <dwayne@zeroc.com> | 2008-06-04 14:01:55 -0230 |
| commit | 9f098cbf76628e94ea337ab9adb2407b705f97f6 (patch) | |
| tree | fc75eef868f7ae8fdd20c5b1c55eb42e9562d7d6 /cppe/include | |
| parent | Fixed clean target in casino demo (diff) | |
| download | ice-9f098cbf76628e94ea337ab9adb2407b705f97f6.tar.bz2 ice-9f098cbf76628e94ea337ab9adb2407b705f97f6.tar.xz ice-9f098cbf76628e94ea337ab9adb2407b705f97f6.zip | |
Bug 3168 - better endian detection
Diffstat (limited to 'cppe/include')
| -rw-r--r-- | cppe/include/IceE/Config.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/cppe/include/IceE/Config.h b/cppe/include/IceE/Config.h index 8fc9e62d211..6367a27a3a4 100644 --- a/cppe/include/IceE/Config.h +++ b/cppe/include/IceE/Config.h @@ -103,12 +103,17 @@ // Most CPUs support only one endianness, with the notable exceptions // of Itanium (IA64) and MIPS. // +#ifdef __GLIBC__ +# include <endian.h> +#endif + #if defined(__i386) || defined(_M_IX86) || defined (__x86_64) || \ defined (_M_ARM) || defined(__MIPSEL__) || defined (__ARMEL__) || \ - defined (__BFIN__) + defined (__BFIN__) || (defined(__BYTE_ORDER) && (__BYTE_ORDER == __LITTLE_ENDIAN)) # define ICE_LITTLE_ENDIAN #elif defined(__sparc) || defined(__sparc__) || defined(__hppa) || \ - defined(__ppc__) || defined(_ARCH_COM) || defined(__MIPSEB__) + defined(__ppc__) || defined(_ARCH_COM) || defined(__MIPSEB__) || \ + (defined(__BYTE_ORDER) && (__BYTE_ORDER == __BIG_ENDIAN)) # define ICE_BIG_ENDIAN #else # define ICE_LITTLE_ENDIAN |